The present invention relates to a digital circuit, and more particularly to a precharge circuit for a digital circuit employing field-effect transistors.
Digital circuits widely adopt the precharge technique in which predetermined circuit nodes are all charged to a predetermined potential. Subsequently, charges accumulated at the selected circuit nodes are discharged to determine logic levels. This precharge technique is advantageous in that there is low power consumption and high speed operation.
For example, in a memory circuit, a plurality of digit lines to which memory cells are connected, are precharged from a precharge voltage source through precharge transistors coupled between the respective digit lines and the precharge voltage source prior to each operation. In performing the precharge, a precharge control signal is commonly applied to the precharge transistors. The precharge control signal is usually generated as an output signal of an inverter which receives a basic control signal such as a chip enable signal and with a predetermined slope it changes from the one of the binary logic levels which makes the precharge transistors non-conducting to the other of the binary logic levels which makes the precharge transistors conducting.
When the precharge control signal changes from the above one of the binary logic levels towards the other of the binary logic levels, a potential at the gates of the precharge transistors similarly changes and the precharge transistors become conducting to feed circuit nodes such as digit lines with currents. The potential at the circuit nodes to be charged is gradually raised as time elapses. This raise of potential at the circuit nodes functions to reduce the gate-source voltage bias of the precharge transistors. Therefore, amount of currents fed through the precharge transistors is increased in accordance with the shift in potential of the precharge control signal towards the other of the binary logic levels until a predetermined time point. It is then decreased in accordance with the potential raise at the circuit nodes to be charged. Accordingly, the amount of current fed throughout the precharge inevitably takes a peak value. In general, if a current having a large peak value flows in a circuit, then various harmful noises are generated and in the worst case malfunction of the circuit would be caused.
In order to reduce the peak value of the current, conductances of the precharge transistors could be reduced. Also, the rate at which the precharge voltage is applied can be reduced to moderate the peak value of the precharge current. However, if this technique were employed, there would be a disadvantage in that the time required for completing the precharge would be prolonged, resulting in a low speed operation.
It is one object of the present invention to provide a precharge circuit in which the peak value of a charging current can be made small without prolonging the charging time.